· Digitally Enabled Phase Locked Loop
Phase locked loop (PLL) plays an important role in almost every electronic system for synthesizing clocks at the desired frequencies. The conventional analog PLL requires bulky charge pump / loop filter, which increases the design difficulty in the scaled technology. The emerging trend of PLL is to leverage DSP techniques to substantially reduce its implementation cost (area/power) while achieving a high flexibility. The goal of this project is to explore signal processing techniques to further reduce the PLL cost.
· Time-Based Circuits
Time domain information plays an important role in various mixed-signal circuit blocks, where time measurement is required. The goal of this research project is to explore new applications and circuit architectures by leveraging time-to-digital or digital-to-time conversion.
· Asynchronous Analog-to-Digital Converter
Conventional ADC utilizes synchronous sampling and internal processing to convert the analog signal into digital representations. Instead, this research project aims to convert the analog signal via asynchronous sampling and processing and explore its unique properties to enable potentially new analog-to-digital conversion architectures.