Analog Mixed-Signal IC Group

Mike Chen


· High-Speed Low-Power Analog-to-Digital Converter

High-speed low-power analog-to-digital converter is crucial for various applications and can potentially enable new system architectures with high flexibility.  Reduction of minimum feature size in CMOS as well as scaling of supply voltage provide a favorable platform for digital designs.  This research project is to explore various digital signal processing and mixed-signal techniques to advance the power efficiency of the ADC in the high-speed (>GHz), and high-resolution regime.  The photos shown below are the recent ADC prototype in 65nm CMOS and test board.

· High-Speed Digital-to-Analog Converter

The high-speed DAC (>GHz) has been traditionally constrained by SFDR, at high input frequencies. The goal of this research project is to explore mixed-signal techniques to advance the DAC performance in the high sampling speed regime.


· Circuit Reliability

As the MOS technology scales down, the circuits suffer performance degradations due to the device breakdown triggered by well-known aging effects including NBTI, CHC and TDDB. The goal of this research project is to understand the impact of those aging effects on analog circuits and acquire the insight to realize more robust circuit architecture.  The photos shown below are the recent silicon test structures and test setup.


· Digitally Enabled Phase Locked Loop 

Phase locked loop (PLL) plays an important role in almost every electronic system for synthesizing clocks at the desired frequencies.   The conventional analog PLL requires bulky charge pump / loop filter, which increases the design difficulty in the scaled technology.   The emerging trend of PLL is to leverage DSP techniques to substantially reduce its implementation cost (area/power) while achieving a high flexibility.  The goal of this project is to explore signal processing techniques to further reduce the PLL cost.


· Time-Based Circuits

Time domain information plays an important role in various mixed-signal circuit blocks, where time measurement is required.  The goal of this research project is to explore new applications and circuit architectures by leveraging time-to-digital or digital-to-time conversion.


· Asynchronous Analog-to-Digital Converter

Conventional ADC utilizes synchronous sampling and internal processing to convert the analog signal into digital representations.  Instead, this research project aims to convert the analog signal via asynchronous sampling and processing and explore its unique properties to enable potentially new analog-to-digital conversion architectures. 


Future electronic system demands and technology improvements are driving the circuit community towards wider bandwidth, faster speed and yet lower power/cost. Inspired by this growing trend, our current research activities focus on exploring the limit of various analog-to-digital interface circuits that will substantially advance the existing circuit and system architecture.  Meanwhile, we explore the increasingly important technology reliability issues that will affect analog circuits design.  The ultimate goal is to make better, cheaper and more robust circuits and systems.