Analog Mixed-Signal IC Group

Mike Chen

Goal

    Our research goal is to explore the optimal analog circuit and system architecture with diminishing power and area consumption in the future nano-scale technologies.  In many cases, we aim at reshaping the analog and digital boundary of the circuit/system architecture, and leveraging what technology scaling offers to address the future analog design challenges.

 

    At the circuit level, we are interested in pushing the boundary of various critical analog mixed-signal, RF components, such as data converters (ADC, DAC), phase locked loop (PLL) frequency synthesizer, etc.  At the system level, we are also interested in wireless/wireline communication systems and emerging applications, such as bio-related, sensing systems, computing platform (machine learning/artificial intelligence/neural network).

LATEST News

We are hiring highly motivated PhD students. 

We welcome Industrial/research institution collaborations.

OPENINGs

· Aug 2014

Dr. Chen recently gives a tutorial on “Asynchronous SAR ADC: Past, Present and Beyond”. The slides can be downloaded here [pdf].

· Dec. 2012

Dylan Hand presented a new non-uniform ADC architecture at Globecom Dec. 2012. Congrats, Dylan!

· July 2013

Praveen Sharma will present a new Nyquist VCO-based ADC architecture at CICC Sep, 2013. It achieves >400MHz bandwidth for the first time among published VCO-based ADC. Congrats, Praveen!

· July 2013

Jaewon Nam will present a new asynchronous SAR ADC architecture with passive gain stage at CICC Sep, 2013, achieving the best Figure-of-Merit (J/conv-step) in its class (up to date) .  Congrats, Jaewon!

· Feb 2014

Cheng-Ru Ho will present the first digital PLL architecture with adaptive spur cancellation technique and low-cost time-to-digital conversion at RFIC 2014. It achieves unprecedented spur rejection by >40dB (measured data). Congrats, Cheng Ru!

· March 2014

Shiyu Su will present the first hybrid DAC architecture with delta-sigma assisted pre-distortion technique at VLSI Symposium 2014. This DAC achieves the new record linearity among all published high-speed (>GS/s) CMOS DACs (up to date). Congrats, Shiyu and the team!

· Sep 2015

Tzu Fan Wu presented the first Flash-based Non-Uniform Sampling ADC architecture at CICC 2015. This ADC architecture provides new opportunity to perform anti-aliasing filtering in the digital domain. Congrats, Tzu Fan and the team!

· Nov 2015

Cheng Ru Ho will present a new fractional-N digital PLL architecture with feedforward multi-tone cancellation at ISSCC 2016. This PLL achieves new record low reference spur (<-110dBc) and in-band fractional spurs (<-73dBc) compared to any published analog or digital PLL.  This work provides new design direction for future PLLs, beyond what existing PLLs can do. Congrats, Cheng Ru!

 

 

· Nov 2015

Shiyu Su will present a new timing and noise cancellation scheme for dual-rate hybrid DAC (with 1GHz bandwidth) at ISSCC 2016. This DAC achieves new record SFDR and IM3 compared to any high-speed CMOS DAC.  Congrats, Shiyu!

 

 

· Mar 2016

Jaewon Nam will present a 12-b 1.6GS/s dual reference multi-bit SAR architecture at VLSI 2016. This ADC achieves record  ENOB and power efficiency for GHz signal bandwidth compared to previously published ADCs.  Congrats, Jaewon, Aoyang and Mohsen!

 

 

· Dec 2016

Cheng-Ru Ho receives Predoctoral Achievement Award from IEEE Solid-State Circuits Society. Congrats, Cheng Ru!

 

 

· Dec 2017

Shiyu Su receives Predoctoral Achievement Award from IEEE Solid-State Circuits Society. Congrats, Shiyu!

 

 

· Nov 2017

Cheng-Ru Ho will present a dither-assisted pulling mitigation at ISSCC 2018 for mitigating the interference coupling from both DCO and reference Path simultaneously for the first time. Congrats, Cheng Ru!

· Nov 2017

Tzu-Fan Wu receives Best Poster Award at 8th Annual EE Research Festival among 80 poster presenters from USC EE department.  Congrats, Tzu Fan!

 

 

· Nov 2017

Cheng-Ru Ho will present a background dither noise cancellation loop at ISSCC 2018 for mitigating near carrier fractional spurs. Congrats, Cheng Ru!

· Nov 2017

Shiyu Su will present a flexible bandpass hybrid DAC architecture at ISSCC 2018 for synthesizing high-fidelity signal within DC to 6GHz tunable passbands.  Congrats, Shiyu!

· June 2017

Rezwan Rasul will present a Time multiplexed architecture for large-scale neuromorphic computing at MWSCAS 2017. Congrats, Rezwan and Pedram!

· June 2016

Cheng-Ru Ho will present a DCO Spur mitigation scheme at ESSCIRC 2016. Congrats, Cheng Ru!